A Novel Logic Element for Power Reduction in FPDs

Although many techniques have been proposed for power reduction in fieldprogrammable devices (FPDs), they are all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the lookup table (LUT) in many FPGAs) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when it is not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel low power LE. The differences between our LE and the conventional LE are in the type of flip-flops used and the internal organization. Instead of using DFFs, we use T flip-flops with the input T permanently connected to logic value one. Instead of connecting the output of the combinational logic to the input of the FF, we connect it to the clock input of the FF. Transistor-level circuit simulations on MCNC benchmark circuits indicate that the FPD using the proposed LEs not only consumes up to 42% less total power by avoiding the unnecessary activities of the clock, logic, and interconnect, but performs up to 33% faster than the FPD using conventional LEs.